Pipelining techniques can be used in a DSP system to enhance processing speed at a critical path of the circuit structure or to reduce power consumption at the same processing speed in the DSP system. By allowing different functional units to operate concurrently, DSP pipelining can increase the throughput of the DSP system when processing a stream of tasks.
One example application of a pipelined DSP system can be the implementation of FIR filters. As the FIR filter circuit usually involves a number of registers, an enabling signal or a clock signal is usually fed into each register to control the register operation. A flat enable arrangement can be used to have one enable signal directly connected to every register in the FIR filter. When the FIR filter is large or complex in scale, is implemented in a deeply pipelined DSP block, or is combined with other FIR filters as part of a larger system, the increased fan-out requirement associated with the flat enable arrangement affects performance of the circuit. For example, the high fan-out of the enable line usually requires additional resources such as additional power consumption to implement the high fan-out, as well as routing for the enable signal (which may consume additional general-purpose programmable logic resources when the FIR filter is implemented in a programmable integrated circuit such as a field-programmable gate array (FPGA) or other programmable logic device (PLD).